1. Field of the Invention
The present invention relates to a voltage supplying device, and a semiconductor device, an electro-optical device and an electronic instrument using the voltage supplying device.
2. Description of Related Art
In recent years, there are devices requiring a highly accurate voltage supply, for example, a liquid crystal display.
In an active matrix type of liquid crystal display or a simple matrix type of liquid crystal display, the number of grayscales (or colors) of a liquid crystal panel is highly improved, and a voltage to be applied is developed to be more precise.
In order to increase the number of grayscales of a liquid crystal panel, a thin film transistor (TFT) liquid crystal device which is an active matrix type of liquid crystal display uses three colors of RGB (red, green and blue) which includes data signals constituted of 6-bit data (64 grayscales, ca. 260,000 colors) or 8-bit data (256 grayscales, ca. 16,770,000 colors), for example.
With the increase in the number of grayscales, a technique of setting a voltage level more precisely is required.
According to the characteristics in relationship between the applied voltage and the panel transmittance of a liquid crystal panel, the rate of change in panel transmittance with respect to the applied voltage is large where the transmittance is in the middle level around 50%, and is decreased when the panel transmittance approaches 100% or 0%. Therefore, in the region where the panel transmittance is in the middle level, a slight deviation in the applied voltage has a great influence on a gray level. In order to suppress the change in panel transmittance, a voltage to be applied to liquid crystal is required to be supplied more precisely.
The maximum permissible level in dispersion of a voltage to be applied to liquid crystal is ±5 mV for 64 grayscales and ±1 to ±2 mV for 256 grayscales, for example, and more precise voltage is required to be applied to liquid crystal when the number of grayscales is increased. Although the dispersion in the threshold voltage VTH of an ordinary IC chip is allowed to range from several tens mV to several hundreds mV, a liquid crystal display with the increased number of grayscales has a severer maximum permissible level. It can be predicted that further increase in the number of grayscales in future requires more precise setting method for a voltage to be applied to liquid crystal.
Consequently, there are conventionally various method of generating grayscale voltages in a driving circuit of a liquid crystal panel, such as a voltage selecting method, a time sharing method, or a digital-analog conversion method.
FIG. 4 shows a conventional voltage supplying device of the method using a digital-analogue conversion device (hereinafter referred to as a DAC method).
A voltage follower circuit 72, into which an output from a DAC 70 is entered, functions as an impedance converter, and in the case of a voltage follower circuit 72 in an ideal state, a voltage of a node 201 entered into a non-inverse input terminal becomes equal to a voltage of a node 202 entered into an inverse input terminal. However, conventionally in the voltage follower circuit 72 not compensated by an offset canceling circuit, an offset is formed between the input and the output due to dispersion in performance of respective transistors, so as to form a difference in voltage between the node 201 and the node 202.
FIG. 4 shows a voltage supplying device for solving the problem. The output from the DAC 70 is supplied to the non-inverse input terminal 201 of the voltage follower circuit 72, and the output of the voltage follower circuit 72 is returned to the inverse input terminal 202. In the course of the circuit connecting the output line and the non-inverse input terminal 201, a switching element Q10, a capacitance C10 and a switching element Q12 are connected in series. On the negative feedback line connected to the inverse input terminal 202, only a switching element Q1 is present. The switching element Q10 is connected in parallel to the capacitance C10 and the switching element Q11.
In a first period, the switching element Q11 is off, and the switching element Q10 and the switching element Q12 are on, whereby an offset voltage between the input and the output of the voltage follower circuit 72 is charged in the capacitance C10. In a second period, the switching element Q11 is on, and the switching element Q10 and the switching element Q12 are off, whereby a charge of offset canceling charged in the capacitance C10 is superposed and returned to the inverse input terminal 202 of the voltage follower circuit 72.
According to the foregoing manner, the offset is cancelled out by applying a reverse voltage corresponding to the offset in such a manner that the capacitance C10 for offset canceling is provided on the circuit connecting the output line and the non-inverse input terminal 201 of the voltage follower circuit 72.
In the data driver of the conventional DAC method shown in FIG. 4, the capacitance C10 as the offset canceling circuit is necessarily housed in the chip. However, it requires a large area since the capacitance C10 having a sufficiently larger capacity than the input capacity of the voltage follower circuit 72. When the offset canceling capacity is too small, it is regarded as a noise in the input capacity of the voltage follower circuit 72, and thus the noise is superposed on the output voltage.
Furthermore, in order to charge the offset voltage in the offset canceling capacitance C10, a period of time of from 3 to 5 μs is generally required.
In the active matrix type of liquid crystal display of these kinds, the horizontal scanning period (select period) is necessarily set at a short period when high definition display is conducted by increasing the number of pixels in one line.
For example, the select period becomes as short as from 8 to 12 μm in high definition display of SXGA.
In this case, it becomes difficult to assure a period of time for offset canceling when the period for charging the capacitance C10 for offset canceling occupies the select period.